1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a burst ordering operation of a semiconductor device.
2. Description of the Related Art
In general, a semiconductor memory element such as a double data rate synchronous DRAM (DDR SDRAM) receives various commands in synchronization with an external clock, operates in synchronization with an internal clock, and outputs data as a result of memory operations.
As described above, when the semiconductor memory element outputs data, a burst ordering operation may be performed for a critical word first (CWF) operation.
The burst ordering operation represents an operation for designating an output order of data to be output corresponding to the size of a burst length of a semiconductor device.